The present invention relates to a method of generating an interface between circuit blocks in designing a large-scale semiconductor integrated circuit device by using circuit blocks, which are existing resources for designing a circuit such as IPs (Intellectual Properties).
To reduce the number of designing steps, the development of such a large-scale integrated circuit device as termed, e.g., xe2x80x9csystem LSIxe2x80x9d using circuit blocks termed IPs (or IP cores), which are existing resources for designing a circuit, has been started recently. The circuit blocks have predetermined input/output interfaces (I/F) which are normally different from one circuit block to another. In incorporating such circuit blocks having different interfaces into one system, therefore, it is an important design issue how to adjust the I/F of the individual circuits blocks and thereby promote smooth signal transmission between the individual circuit blocks. For example, it is necessary to modify logics and timings for I/F adjustment in incorporating the circuit blocks into one system.
To meet the necessity, a designing operation has been performed conventionally by a designer who recognizes input/output logics and timings of the circuit blocks, fully understands the difference in I/F structure between the individual circuits blocks, and newly designs an interface circuit or the like required to incorporate the circuit blocks such that the difference in I/F structure between the individual circuit blocks is absorbed and the connecting states between the individual circuit blocks are retained.
As a system LSI to be designed has been scaled up increasingly in recent years, however, the number of circuit blocks to be incorporated into the system LSI has also been increased exponentially. If an adjustment between the individual circuits is performed manually, an enormous amount of designing operation should be performed. In other words, it has been becoming difficult to efficiently design a large-scale integrated circuit device such as a system LSI by a conventional designing method which depends only on the skills of the designer.
On the other hand, there has been known such technology as follows which focuses attention on circuit behaviors such as the attributes and timings of signals and generates a new circuit from the circuit behaviors.
For example, Japanese Unexamined Patent Publication No. HEI 6-32972 discloses technology for generating a new hardware description language from a timing chart and the attributes of signals.
Japanese Unexamined Patent Publication No. HEI 7-253998 discloses technology for synthesizing, by using a truth table, behavioral descriptions of two or more logic circuits newly generated and thereby producing a new, complete circuit behavioral description.
Japanese Unexamined Patent Publication No. HEI 9-91355 discloses technology for generating circuit data, expected value data, timing data, or the like based on operational data, performing simulation, and automatically generating a new logic circuit.
In view of the foregoing, there can be considered the generation of a circuit for absorbing a difference in I/F structure between the circuit blocks by using the conventional methods of automatically generating circuits mentioned above.
Although the technology disclosed in the foregoing conventional publications allows generation of a new circuit block independent of the circuit blocks, the matter of how to smoothly retain the connecting states between the individual blocks remains to be solved. With the conventional technologies, it is difficult to generate an interface circuit considering a difference in I/F structure between the individual circuit blocks in the design of an integrated circuit device using circuit blocks which are existing resources.
It is therefore an object of the present invention to improve, in the design of an integrated circuit device using circuit blocks which are existing resources, an efficiency with which a large-scale integrated circuit device is designed with the provision of means which allows easy correction or modification of an existing circuit considering an interface structure and easy generation and insertion of a new interface circuit between circuit blocks without recognizing the input/output logics, timings, and the like of the circuit blocks.
A first method of designing a semiconductor integrated circuit device of the present invention is a method of designing a semiconductor integrated circuit device by using at least two circuit blocks stored in a database, the method comprising the steps of: (a) generating an interface circuit for implementing, in response to an operation of modifying a timing chart for providing a coincidence between a timing relationship between input signals or output signals of a first circuit block and a timing relationship between input signals or output signals of a second circuit block, a content of the modification in the timing chart; and (b) automatically inserting the interface circuit generated in the step (a) between the first and second circuits.
If a semiconductor integrated circuit device is to be constructed by using a plurality of circuit blocks such as IPs having different timing characteristics, the method allows automatic insertion of an interface circuit for providing smooth transmission of data between the circuit blocks. Accordingly, the number of designing steps is reduced greatly and a designing method suitable for the construction of a large-scale semiconductor integrated circuit device, such as a system LSI, is provided.
A second method of designing a semiconductor integrated circuit device of the present invention is a method of designing a semiconductor integrated circuit device by using at least two circuit blocks stored in a database, the method comprising the steps of: (a) generating an interface circuit for implementing, in response to an operation of modifying a timing chart for providing a coincidence between a timing relationship between input signals or output signals of a first circuit block and a timing relationship between input signals or output signals of a second circuit block, a content of the modification in the timing chart; and (b) adding the interface circuit generated in the step (a) to the first or second circuit block.
If a semiconductor integrated circuit device is to be constructed by using a plurality of circuit blocks such as IPs having different timing characteristics, the method allows generation of a new circuit block by adding, to the circuit block, an interface circuit for providing smooth transmission of data between the circuit blocks. Consequently, the number of designing steps is reduced greatly, while the number of components required to design the semiconductor integrated circuit device is reduced, so that a designing method suitable for the construction of a large-scale semiconductor integrated circuit device, such as a system LSI, is provided.
The second method further comprises the step of: storing, in the database, the first or second circuit block having the interface circuit added thereto as a new circuit block. This allows the corrected circuit block to be re-used to design another semiconductor integrated circuit device.
The step (b) includes determining either of the first and second circuits as the circuit to which the interface circuit is to be added based on a preset parameter. This allows the designing of a semiconductor integrated circuit device in which the parameter to which the user attaches importance is optimized.
The step (b) includes using a layout area as a parameter. This allows design even conscious of layout.
The step (b) includes using, as a parameter, a variation in a number of pins in the first or second circuit block. This allows design conscious of the number of pins.
If at least one other circuit block in addition to the first and second circuit blocks is disposed in the integrated circuit device, the step (b) includes using, as a parameter, a number of circuit blocks to each of which the interface circuit is added. This minimizes the number of circuit blocks to be corrected.
A third method of designing a semiconductor integrated circuit device of the present invention is a method of designing a semiconductor integrated circuit device by using a database, the method comprising the steps of: (a) storing, upon receipt of an operation of modifying a waveform of a signal extracted from the database on a display screen, a waveform of the signal after the modification in storing means; (b) extracting data stored in the storing means and converting the modification in the waveform to a circuit behavior based on a difference between the waveforms before and after the modification; and (c) generating a circuit for performing the circuit behavior.
In accordance with the method, a process of transforming a signal waveform such as movement or inversion in designing a semiconductor integrated circuit device can be performed easily by using a GUI. This allows a process necessary for designing, such as the addition of an element or the correction of a circuit block, to be performed promptly.
The third method may further comprise the step of: inserting the circuit generated in the step (b) as an interface circuit between circuit blocks.
The step (c) selectively includes generating the circuit at an RT level, at a gate level, in a programming language for describing a function, the programming language having no conception of time, or in a programming language for describing a function in a cycle behavior, the programming language having a conception of time. This renders the present invention applicable to simulation performed by using a hardware simulator and a hardware-software co-design/verification tool.
A fourth method of designing a semiconductor integrated circuit device of the present invention is a method of designing a semiconductor integrated circuit device by using a database, the method comprising the steps of: (a) storing, upon receipt of an operation of modifying a waveform of a signal extracted from the database on a display screen, a waveform of the signal after the modification in storing means; (b) extracting data stored in the storing means and judging whether or not the waveform after the modification is coincident with a desired waveform; and (c) displaying, if the waveform after the modification is not coincident with the desired waveform, a statement that the desired waveform cannot be generated.
The method reduces the time required to search a portion that cannot be generated and analyze the reason that the portion cannot be generated in performing a process for obtaining the desired waveform.
A portion of the desired waveform that cannot be generated is displayed on the display screen simultaneously with or after the step (c). This allows the user to properly judge a method of generating a signal corresponding to the portion that cannot be generated and enables rapid generation of an optimum circuit.
The fourth method further comprises the steps of: (d) extracting a part of a waveform of each of a plurality of signals extracted from the database which corresponds to one cycle of a clock to generate a rising portion of the portion that cannot be generated; and (e) prior to or after the step (d), extracting a part of a waveform of each of a plurality of signals extracted from the database which corresponds to one cycle of the clock to generate a falling portion of the portion that cannot be generated. This allows easy generation of the waveform the generation of which has been once judged to be impossible.
A fifth method of designing a semiconductor integrated circuit device of the present invention is a method of designing a semiconductor integrated circuit device by using a database, the method comprising the steps of: (a) extracting a part of a waveform of each of a plurality of signals extracted from the database which corresponds to one cycle of a clock to generate a rising portion of a desired waveform or waveform portion; and (b) prior to or after the step (a), extracting a part of a waveform of each of a plurality of signals extracted from the database which corresponds to one cycle of the clock to generate a falling portion of the desired waveform or waveform portion.
The method allows the desired waveform to be generated easily by using a simple operation.
The step (b) includes a process of moving an entire waveform in an interval interposed between the rising and falling portions that have been generated. This allows more flexible generation of the waveform.
A sixth method of designing a semiconductor integrated circuit device of the present invention is a method of designing, by using a database having first and second circuit blocks designed to operate with first and second clocks with different frequencies, a semiconductor integrated circuit device in which the first and second circuit blocks are disposed in preceding and following stages, respectively, the method comprising the steps of: (a) judging whether or not the frequency of the first clock is equal to or longer than double the period of the second clock; (b) if the frequency of the first clock is equal to or longer than double the frequency of the second clock, detecting an edge of the first clock by using the second clock; (c) inserting an interface circuit for supplying, as an operation enable signal, a signal generated by detecting the edge to the second circuit block; and (d) modifying a description of the second circuit block such that the second circuit block operates in response to the operation enable signal supplied from the interface circuit.
The method smoothes transmission of data between the two circuit blocks operating with the clocks having different frequencies by a simple process. As a result, data can be passed smoothly and a restriction imposed on selection by the type of a clock for an IP core to be used is reduced so that the design is accelerated by a wider range of choices and the quality of the designed semiconductor integrated circuit device is improved.
If the period of the first clock is judged to be longer than the period of the second clock and shorter than double the period of the second clock in the step (a), the step (d) can be performed after the first clock is used as the operation enable for the second circuit block.
If the period of the first clock is judged to be shorter than the period of the second clock in the step (a), the sixth method preferably further comprises the step of: displaying a statement that the interface circuit cannot be generated.
If a third block extracted from the database and operating with the first clock is disposed in the following stage of the second circuit block, the sixth method preferably further comprises the step of: modifying a description of the second circuit block to synchronize a period of an output data signal outputted to the third circuit block with the enable signal.
A seventh method of designing a semiconductor integrated circuit device of the present invention is a method of designing, by using a database having first and second circuit blocks, a semiconductor integrated circuit device in which the first and second circuit blocks are disposed in preceding and following stages, respectively, the method comprising the steps of: (a) selecting a data signal in a timing chart for the first circuit block and detecting a data transition region; (b) receiving the data signal from the first circuit block and automatically generating a first margin nearly equal to a hold time and a second margin nearly equal to a set-up time anterior and posterior to the data transition region, respectively; and (c) inserting, between the first and second circuit blocks, an interface circuit for generating a data defining signal having, as data non-valid periods, respective periods anterior and posterior to the data transmission region to which the first and second margins have been set and having the other periods as data valid periods, wherein the data signal is transferred from the first circuit block to the second circuit block and the second circuit block fetches the data by using the data defining signal.
In designing a semiconductor integrated circuit device constructed by laying out a large number of circuit blocks in accordance with the method, the data defining signal is generated by focusing attention on the data transmission region and without using a synchronizing signal (such as clock) for the generation of the data defining signal. As a result, the data defined interval can be indicated without being affected by the relationship between the clock frequencies used by the transmitting/receiving blocks. This allows efficient use of transferred data even in a non-synchronous circuit interface. This further saves the designer the burden of designing an interface circuit including complicated timing control.
An eighth method of designing a semiconductor integrated circuit device of the present invention is a method of designing, by using a database having first and second circuit blocks, a semiconductor integrated circuit device in which the first and second circuit blocks are disposed in preceding and following stages, respectively, the method comprising the steps of: (a) generating a first delay circuit for receiving a first data signal outputted from the first circuit block and outputting a second data signal which has been delayed by a first margin nearly equal to a hold time; (b) generating a second delay circuit for receiving the second data signal and outputting a third data signal which has been delayed by a second margin nearly equal to a set-up time; and (c) inserting, between the second delay circuit and the second circuit block, a circuit for receiving the first and third data signals and generating a data defining signal which becomes invalid at a starting point of a data transition region of the first data signal and becomes valid at an ending point of a data transition region of the third data signal, wherein the second data signal is transferred to the second circuit block and the second circuit block fetches the data by using the data defining signal.
In designing a semiconductor integrated circuit device constructed by laying out a large number of circuit blocks, the method also achieves the same effects as achieved by the seventh method of designing a semiconductor integrated circuit device by generating, by focusing attention on the data transition region, a data defining signal without using a synchronizing signal for the generation of the data defining signal.
A ninth method of designing a semiconductor integrated circuit device of the present invention is a method of designing, by using a database having first and second circuit blocks, a semiconductor integrated circuit device in which the first and second circuit blocks are disposed in preceding and following stages, respectively, the method comprising the steps of: (a) extracting a timing chart for a signal having a desired waveform from the second circuit block and searching a signal having the same waveform in the first circuit block; (b) combining, if there is no signal having the desired waveform in the first circuit block, a plurality of signals in the second circuit block to generate an interface circuit for outputting a signal having the same waveform as the desired waveform; and (c) modifying a description of the second circuit block such that an output of the interface circuit is inputted as a desired signal.
In accordance with the method, even if it is difficult to obtain the desired waveform since the content of the preceding first circuit block is unknown to the following second circuit block, the desired waveform can be obtained by constructing the interface circuit by combining signals in the second circuit block.
By setting an upper limit value of a number of the plurality of combined signals, a search time is prevented from becoming indefinitely long.
The step (b) includes generating the interface circuit as a sequential circuit by adding a sequential element to at least any one of the plurality of signals. This further increases the probability of generating the desired waveform.
By setting an upper limit value of a number of stages in the sequential element, the search time is prevented from becoming indefinitely long.
The step (b) includes generating the interface circuit by extracting a signal from a node in the first circuit block and combining the signal from the node with the plurality of signals and a description of the first circuit block is modified such that a function of outputting the signal from the node is added. This further increases the probability of generating the desired waveform.
A tenth method of designing a semiconductor integrated circuit device of the present invention is a method of designing, by using a database having first, second, and third circuit blocks, a semiconductor integrated circuit device in which the first, second, and third circuit blocks are disposed successively in an upstream-to-downstream direction, the method comprising, in producing a logic synthesis script for a logic synthesis of the second circuit block, the steps of: (a) extracting a waveform of an output signal of the first circuit block, a waveform of an input signal of the third circuit block which receives the output signal of the first circuit block, and a waveform of a clock for the second circuit block; (b) inserting, in the logic synthesis script, a description for setting a delay time for each of the output signal of the first circuit block and the input signal of the third circuit block; and (c) inserting, in the logic synthesis script, a description for setting a clock period for the second circuit block.
If the logic synthesis of a certain circuit block is to be performed, the method allows a logic synthesis script for the circuit block to be generated automatically in consideration of data on delays in the circuit block and in other circuit blocks connected anterior and posterior thereto. As a result, the number of designing steps is reduced and the quality of the designed semiconductor integrated circuit device is increased.